IBIS Macromodel Task Group

Meeting date: 15 aug 2006

Members (asterisk for those attending):
*Arpad Muranyi, Intel Corp.
*Barry Katz, SiSoft
*Bob Ross, Teraspeed Consulting Group
*Doug White, Cisco Systems
*Ian Dodd, Mentor Graphics
*Joe Abler, IBM
John Shields, Mentor Graphics
Ken Willis, Cadence Design Systems
Kumar, Cadence Design Systems
*Lance Wang, Cadence Design Systems
*Michael Mirmak, Intel Corp.
*Mike LaBonte, Cisco Systems
Paul Fernando, NCSU
*Randy Wolff, Micron Technology
*Richard Ward, Texas Instruments
Sanjeev Gupta, Agilent
*Todd Westerhoff, Cisco Systems
Walter Katz, SiSoft

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Review of ARs:

- Ian invite a SystemC expert to speak to us about APIs

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New Discussion:

Last week we discussed meeting time and group name.
- Decided to keep this time slot
- Name: Advanced Modeling Task Group

When will Gary Pratt be able to present to our group?
- Is Gary Pratt a Mentor employee or in some other business?
- Gary says there are ways to model other than convolution simulation.
- Ian: lot of commonality between EDA companies
  - Linear time domain simulators can simulate millions of cycles quickly.
  - IBM has proposed binary models
  - Cadence has proposed binary API strictly for linear simulators
    - Simulator provided under NDA to customers using IBM models
    - Multi-step process:
      1 - get impulse response
      2 - convolution simulation
      3 - extrapolate to 10e18 bits (Richard)

What to call the 2 simulator styles:
- Old style: non-linear (Ian), circuit (Kumar)
- New style: convolution, linear (Ian), signal (Kumar)

What are we trying to do?
- Predict channel out to 10e20 bits

What is IBM doing?
- Simulator assumes linearity
- Simulates at circuit level, not device level.
- Initial impulse response simulation has to be non-linear.
- Can do 10 million bits in 15 minutes on a reasonably fast PC.
- SPICE can't handle this.
- Writing in C to include control algorithms (could be Matlab)

Michael Mirmak asked if the debate is over performance.

Todd said we need to be able to simulate 1e6 bits, and that HSPICE and
AMS can't do this in a reasonable time, so we are forced into the world
of linear simulation.

Arpad pointed out that AMS has a digital side, which allows certain types of acceleration.

When asked about Mentor Graphics offerings Ian said Mentor doesn't
currently have a linear simulator that includes AMS support.

Mike LaBonte noted that AMS lets you write the model only, and the
simulator engine is written for you, whereas C allows you to control
the actual simulation engine as well as the model, and take advantage
of synergies.

Michael Mirmak believed that we have 2 audiences:
- Algorithm/arch designers who don't have to know hardware.
- AMS designers who design things that have to be validated in the lab.
He also noted that when we are doing power analysis etc. we are stuck
with non-linear simulation.

Ian stated that AMS can do 10s of 1000s of bits per hour in a SPICE
engine, which Todd estimated to yield about a million bits per day.
Richard believed that that would be too slow for architectural design.
Todd felt that no non-linear solution would be able to do an architechture
design, because accuracy issues would limit the ability to trust the
simulations.  Ian suggested people could use linear simulations to find
problems, then non-linear to verify.

Michael Mirmak wondered if we could ask simulator companies to make
simulators recognize linearity in models, and switch modes.

Todd said that a technically capable language is no good if people
won't write in it.

Ian noted that compiler switches would cause platform support problems.
Arpad suggested distributing encrypted source code.

Richard would like to try fixed timestep simulation to improve
performance, but Ian said there are techniques to get good performance
from variable timestep simulation.

Where to next? Michael Mirmak:
- Need a concrete proposal to tackle
- Need a solution now

Someone ??? stated that the Cadence proposal is a point solution, and
Joe asked how it can be made more generic.

Mike LaBonte:
- The IBIS buffer today has digital inputs and analog outputs.
- The Cadence API model has analog in and analog out.
- IBIS can describe the data with only a certain amount of regard
  for how a simulator would use it.
  (Michael Mirmak registered disagreement but we had to end the call then)

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Next meeting: Tuesday 22 Aug 2006 12:00pm PT